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Verification of analog circuits in power-down mode
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Resumo(s)
The energy efficiency and optimization are two important points of analog circuits.
With purpose to reduce the power consumption, most of these circuits are equipped with power-down features, which means the circuits are idle when they are not used.
In power-down mode internal nodes can have floating states which results in an increase
of the transistor degradation.
In this thesis a computer program that checks the node voltage levels and the state of the transistors in power-down mode is presented. The search procedure will ensure that all currents in the paths are safely turned off. The program works just with the structural information of the circuit given into a input file i.e net-list file. No numerical simulation is needed.
Experimental results show the efficacy and efficiency in industrial circuits and also
the integration with the CADENCE software.
Descrição
Dissertação para obtenção do Grau de Mestre em
Engenharia Eletrotécnica e Computadores