New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

Goes, J.; Oliveira, J. P.; Paulino, N.; Fernandes, J.; Paisana, J.

http://hdl.handle.net/10362/4057

Utilize este identificador para referenciar este registo.

Nome:	Descrição:	Tamanho:	Formato:
Goes_2008.pdf		271.5 KB	Adobe PDF	Ver/Abrir

Contacte-nos

Autores

Resumo(s)

In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique.

Descrição

15th IEEE International Conference on Electronics, Circuits and Systems, Malta

URI

http://hdl.handle.net/10362/4057

Editora

IEEE

Coleções

FCT: DEE - Documentos de conferências internacionais

Ver registo completo