Publicação
New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification
| dc.contributor.author | Goes, J. | |
| dc.contributor.author | Oliveira, J. P. | |
| dc.contributor.author | Paulino, N. | |
| dc.contributor.author | Fernandes, J. | |
| dc.contributor.author | Paisana, J. | |
| dc.date.accessioned | 2010-08-12T08:56:58Z | |
| dc.date.available | 2010-08-12T08:56:58Z | |
| dc.date.issued | 2008-08 | |
| dc.description | 15th IEEE International Conference on Electronics, Circuits and Systems, Malta | en_US |
| dc.description.abstract | In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10362/4057 | |
| dc.language.iso | eng | en_US |
| dc.publisher | IEEE | en_US |
| dc.title | New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification | en_US |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| my.embargo.terms | null | en_US |
| rcaap.rights | openAccess | en_US |
| rcaap.type | conferenceObject | en_US |