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An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers
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Resumo(s)
The rapid growth of wireless communications and the massive use of wireless end-user
equipments have created a demand for low-cost, low-power and low-area devices with
tight specifications imposed by standards. The advances in CMOS technology allows,
nowadays, designers to implement circuits that work at high-frequencies, thus, allowing
the complete implementation of RF front ends in a single chip.
In this work, a co-design strategy for the implementation of a fully integrated CMOS
receiver for use in the ISM band is presented. The main focus is given to the Mixer and
the ADC blocks of the presented architecture.
The traditional approach used in RF design requires 50
matching buffers and networks
and AC coupling capacitors between Mixer inputs and LNA and LO outputs. The codesign
strategy avoids the use of DC choke inductors for Mixer biasing, because it is
possible to use the DC level from the output of the LNA and the LO to provide bias to
the Mixer. Moreover, since the entire circuit is in the same chip and the Mixer inputs
are transistors gates, we should consider voltage instead of power and avoid the 50
matching networks.
The proposed ADC architecture relies on a 4-bit flash converter. The main goals are to
achieve low-power and high sampling frequency. To meet these goals, parametric amplification
based on MOS varactors is applied to reduce the offset voltage of the comparators,
avoiding the traditional and power-consuming approach of active pre-amplification gain
stages.
Descrição
Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores