Nanoparticles as a charge trapping layer in Metal-Insulator-Semiconductor structures

Abstract

Memories with floating gate structures are the main device architecture used in current non-volatile memories. Different films for floating gate based devices have been studied to substitute poly-crystalline silicon as the main material in floating gate structures. In current technology tunneling oxides are required to have thicknesses around 30 nm reducing device performance. Nanocrystals and nanoparticles have been emerging as a possible replacement for those films since better retention times and faster devices can be obtained. In this work the study of nanoparticles as the Charge trapping layer was executed. Study of the nanoparticles was made in a MIS structure. Hysteresis loops on C-V curves showing charge trapping was expected. Molybdenum film in the charge trapping layer was characterized as a comparison term for the nanoparticles in the CT-layer. Results of this work detail the importance of the interfacial layers, as well as defects across the oxides, on the electrical characterization of this structures. Hole trapping was achieved with nanoparticles as a charge trapping layer. Data obtained demonstrated the effect of interfacial defects in C-V curves as well as charging behavior in gold nanoparticles and Molybdenum films.