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NMOS based LDO using Recycling Folded Cascode as Error Amplifier
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Este trabalho apresenta um NMOS-LDO convencional robusto implementado em tecnologia FinFet de 16 nm. O LDO apresenta um Recycling Folded CAscode (RFC) como amplificador de erro. Uma simples modificação foi feita no RFC convencional para integrar este OTA no LDO e garantir um circuito robusto. O objetivo principal deste trabalho é alcançar o equilíbrio ótimo entre várias especificações, incluindo ganho DC, Power Supply Rejection (PSR), tempo de resposta e área. A robustez do LDO foi validada sob 516 corners de Processo, Tensão e Temperatura (PVT), assim como através de simulações Monte Carlo (MC). O LDO opera com uma tensão de alimentação que varia de 1.028V a 1.32V e uma tensão de saída que varia de 400mV a 900mV. O regulador deve também ser capaz de fornecer uma corrente de carga de 500𝜇𝐴A a 2mA. Foi realizada uma avaliação extensiva de diferentes topologias, com foco nos seus trade-offs, pontos fortes e fracos sob diferentes correntss de carga e diferentes capacidades na saída. O RFC LDO implementado, que ocupa uma área total de 621.56 𝜇𝑚2 , apresentou um ganho DC médio de 74.9dB, uma PSR média a 10MHz de -16.9dB, uma line/load regulation abaixo de 41 𝜇𝑉/𝑉 e 19 𝜇𝑉/𝑚𝐴, respectivamente, para todos os 516 corners. Além disso, o LDO mantém
consistentemente uma margem de fase superior a 65º, ao mesmo tempo que garante um tempo de startup inferior a 105 ns. Um LDO com um RFC desbalanceado também é estudado e mostrou melhores resultados em PVT, mas pior desempenho em MC. Para eliminar a necessidade de uma tensão de alimentação mais alta no LDO RFC, uma nova arquitetura LDO baseada na estrutura Flipped Voltage Follower (FVF) também é estudada. O LDO proposto é comparado ao estado atual da arte e demonstra um desempenho superior em termos de PSR e line/load regulation. Além disso, alcança a menor tensão de dropout entre todas os LDOs Em termos de eficiência, supera a maioria das arquiteturas tanto em area como consumo de energia.
This work presents a robust conventional NMOS based LDO implemented in 16 nm FinFet technology. The LDO features a recycling folded cascode (RFC) as error amplifier. A simple modification was made to the conventional RFC to integrate this OTA into the LDO and ensure a robust design. The primary objective of this work is to achieve the optimum balance between various specifications including DC gain, Power Supply Rejection, line/load regulation response and silicon area. The robustness of the LDO design was validated at the schematic level under 516 Process, Voltage, and Temperature (PVT) corners, as well as through Monte Carlo (MC) Simulations. The LDO operates with a supply voltage ranging from 1.028V to 1.32V, and an output voltage ranging from 400mV to 900mV. It also should be able to provide a load current of 500𝜇A to 2mA. An extensive evaluation of different topologies was carried out, focusing on their trade-offs, strengths, and weaknesses under high and low current loads and load capacitances. The design RFC LDO, which occupies an area of 621.56 𝜇𝑚2 , demonstrated a mean DC gain of 74.9dB, a mean PSR at 10MHz of -16.9dB, and a line/load regulation bellow 41 𝜇𝑉/𝑉 and 19 𝜇𝑉/𝑚𝐴, respectively, for all 516 corners. Furthemore, the LDO consistently maintains phase margin exceeding 65º, while ensuring a startup time below 105 ns. An LDO with an unbalanced RFC is also studied, and showed improved PVT results but worst MC performance. To eliminate the need for a higher supply voltage in the RFC LDO, a new LDO architecture based on the Flipped Voltage Follower (FVF) structure is studied as well. The proposed LDO is compared to the current state of the art, and demonstrates superior performance in terms of PSR and load/line regulation. Additionally, it achieves the lowest dropout voltage among all designs. In terms of efficiency, it outperforms the majority of architectures in both area and power consumption.
This work presents a robust conventional NMOS based LDO implemented in 16 nm FinFet technology. The LDO features a recycling folded cascode (RFC) as error amplifier. A simple modification was made to the conventional RFC to integrate this OTA into the LDO and ensure a robust design. The primary objective of this work is to achieve the optimum balance between various specifications including DC gain, Power Supply Rejection, line/load regulation response and silicon area. The robustness of the LDO design was validated at the schematic level under 516 Process, Voltage, and Temperature (PVT) corners, as well as through Monte Carlo (MC) Simulations. The LDO operates with a supply voltage ranging from 1.028V to 1.32V, and an output voltage ranging from 400mV to 900mV. It also should be able to provide a load current of 500𝜇A to 2mA. An extensive evaluation of different topologies was carried out, focusing on their trade-offs, strengths, and weaknesses under high and low current loads and load capacitances. The design RFC LDO, which occupies an area of 621.56 𝜇𝑚2 , demonstrated a mean DC gain of 74.9dB, a mean PSR at 10MHz of -16.9dB, and a line/load regulation bellow 41 𝜇𝑉/𝑉 and 19 𝜇𝑉/𝑚𝐴, respectively, for all 516 corners. Furthemore, the LDO consistently maintains phase margin exceeding 65º, while ensuring a startup time below 105 ns. An LDO with an unbalanced RFC is also studied, and showed improved PVT results but worst MC performance. To eliminate the need for a higher supply voltage in the RFC LDO, a new LDO architecture based on the Flipped Voltage Follower (FVF) structure is studied as well. The proposed LDO is compared to the current state of the art, and demonstrates superior performance in terms of PSR and load/line regulation. Additionally, it achieves the lowest dropout voltage among all designs. In terms of efficiency, it outperforms the majority of architectures in both area and power consumption.
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Palavras-chave
NMOS-based Low Dropout Voltage Regulator Recycling Folded Cascode Robust design Transient response Low power circuits