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STUDY AND DESIGN OF A LOW-POWER PHASE-LOCKED LOOP FOR ISM APPLICATIONS
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Orientador(es)
Resumo(s)
Esta dissertação tem como foco o desenvolvimento e implementação de uma Malha de
Captura de Fase (PLL) Analógica de baixa potência como um Sintetizador de Frequência
Inteiro com uma razão de divisão N para aplicações ISM, com especial ênfase na sua
aplicação em sistemas de comunicação LoRa e na sua importância em emissores-receptores
RF.
O modelo do Sintetizador proposto engloba componentes fundamentais, como um
Oscilador LC Controlado por Tensão (VCO), um Detector de Fase e Frequência (PFD) com
base em lógica NOR, uma Bomba de Carga com comutação por porta (CP) e um Filtro
passa-baixo de Segunda Ordem (LF). O VCO apresenta um nível de ruído de fase de
-103.11 dBc/Hz a 1 MHz e atinge um jitter RMS de 14.095 ps. Além disso, a CP fornece
uma corrente de 125 𝜇A. Nesta configuração, são cruciais dois tipos de Divisores: um
Divisor de Frequência, operando com uma topologia TSPC e uma razão de divisão de 128,
e um Divisor em Quadratura colocado à saída do PLL.
O estudo realizado centra-se na análise dinâmica e em condições estacionárias para
determinar a estabilidade e a largura de banda do Sintetizador. O PLL, desenvolvido com
tecnologia CMOS de 130 nm, tem um tempo de bloqueio de 5 𝜇s e uma largura de banda
de 0.73 MHz com um consumo de 3.50 mW, assumindo uma alimentação de 0.9 V. Este
PLL tem uma gama de frequências de 4.864 GHz a 5 GHz, que se estende a 1.736 GHz até
1.738 GHz com o uso de um banco de condensadores de dois bits.
A inclusão do Divisor em Quadratura permite a cobertura da gama de frequências de
868 MHz a 869 MHz e de 2.432 GHz a 2.5 GHz. Tornando o Sintetizador adequado para
ambas as bandas LoRa, tanto a de 2.4 GHz e a de 868 MHz.
Os processos de design e simulação deste trabalho foram realizados com recurso
o software Cadence Virtuoso Design Environment, proporcionando precisão e eficácia
durante o estudo.
This dissertation focuses on developing and implementing a Low-Power Analog Phase- Locked Loop (PLL) as an Integer-N Frequency Synthesiser for ISM applications, with a special emphasis on its application in LoRa communication systems and its importance in RF transceivers. The Synthesiser model presented encompasses several vital components: an LC-Voltage Controlled Oscillator (VCO), a NOR logic-based Phase-Frequency Detector (PFD), a gate- switched Charge Pump (CP) and a Second-order Loop Filter (LF). The VCO showcases a phase noise level of -103.11 dBc/Hz at 1 MHz and achieves an RMS jitter of 14.095 ps, also the CP provides a current of 125 𝜇A. A key feature of this design is the inclusion of two distinct types of Dividers: the first is a Frequency Divider employing a ratioed TSPC topology with a division ratio of 128, while the second is a Quadrature Divider is placed at the output of the PLL. These Dividers play a crucial role in the overall functionality of the Synthesiser. The performed study emphasises both dynamic and steady-state analysis, aiming to evaluate the stability and bandwidth of the Synthesiser. The PLL in focus, which is designed using 130 nm CMOS technology, exhibits a lock time of 5 𝜇s and a bandwidth of 0.73 MHz. It operates with a power consumption of 3.50 mW at a supply voltage of 0.9 V. This PLL has a tuning range that spans from 4.864 GHz to 5 GHz, and it broadens its range to include 1.736 GHz to 1.738 GHz with the use of a two-bit capbank. Including the Quadrature Divider enables frequency coverage from 868 MHz to 869 MHz and 2.432 GHz to 2.5 GHz. This enhancement makes the Synthesiser suitable for both the 2.4 GHz and 868 MHz LoRa bands. This work’s design and simulation processes were conducted using the Cadence Virtu- oso Design Environment software, which provided accuracy and effectiveness throughout the study.
This dissertation focuses on developing and implementing a Low-Power Analog Phase- Locked Loop (PLL) as an Integer-N Frequency Synthesiser for ISM applications, with a special emphasis on its application in LoRa communication systems and its importance in RF transceivers. The Synthesiser model presented encompasses several vital components: an LC-Voltage Controlled Oscillator (VCO), a NOR logic-based Phase-Frequency Detector (PFD), a gate- switched Charge Pump (CP) and a Second-order Loop Filter (LF). The VCO showcases a phase noise level of -103.11 dBc/Hz at 1 MHz and achieves an RMS jitter of 14.095 ps, also the CP provides a current of 125 𝜇A. A key feature of this design is the inclusion of two distinct types of Dividers: the first is a Frequency Divider employing a ratioed TSPC topology with a division ratio of 128, while the second is a Quadrature Divider is placed at the output of the PLL. These Dividers play a crucial role in the overall functionality of the Synthesiser. The performed study emphasises both dynamic and steady-state analysis, aiming to evaluate the stability and bandwidth of the Synthesiser. The PLL in focus, which is designed using 130 nm CMOS technology, exhibits a lock time of 5 𝜇s and a bandwidth of 0.73 MHz. It operates with a power consumption of 3.50 mW at a supply voltage of 0.9 V. This PLL has a tuning range that spans from 4.864 GHz to 5 GHz, and it broadens its range to include 1.736 GHz to 1.738 GHz with the use of a two-bit capbank. Including the Quadrature Divider enables frequency coverage from 868 MHz to 869 MHz and 2.432 GHz to 2.5 GHz. This enhancement makes the Synthesiser suitable for both the 2.4 GHz and 868 MHz LoRa bands. This work’s design and simulation processes were conducted using the Cadence Virtu- oso Design Environment software, which provided accuracy and effectiveness throughout the study.
Descrição
Palavras-chave
LoRa Frequency Synthesiser PLL low-voltage LC-VCO