Publicação
An Ultra Low Power Amplifier-less Sigma-Delta Modulator for Audio Applications
| datacite.subject.fos | Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática | pt_PT |
| dc.contributor.advisor | Paulino, Nuno | |
| dc.contributor.author | Naydenov, Dimo Atanasov | |
| dc.date.accessioned | 2019-07-26T10:47:12Z | |
| dc.date.available | 2019-07-26T10:47:12Z | |
| dc.date.issued | 2019-06 | |
| dc.date.submitted | 2019 | |
| dc.description.abstract | In the current digital age, electronic devices are becoming increasingly more critical, especially mobile devices and "always-listening" devices such as virtual personal assistants. To gather data from the real world, which in this case is voice audio, digital devices need to convert the analog input signals captured by a microphone to a digital stream. The process of data conversion is usually an energy expensive process, where lower power drawing implementations would benefit battery powered devices and provide less energy consuming "always-listening" devices. One of the most appealing Analog to Digital Converter (ADC) implementations are done using Sigma-Delta Modulators ( Ms) due to their use of oversampling that allows the noise to be transferred to higher frequencies that can be posteriorly eliminated by a decimation filter. In discrete time Ms, implemented with Switched-Capacitor (SC), the full capacitor charging consumes a considerable amount of power; to improve this aspect, a partial capacitor charge could be implemented, allowing less energy to be used in each clock cycle. In this thesis, a Multi-stAge Noise SHaping (MASH) 2+1 M is implemented with Metal-Insulator-Metal (MIM) capacitors and Unsilicided P+ Polysilicon resistors with a sampling frequency of 10 MHz and a bandwidth of 20 kHz, to evaluate the practical feasibility of the architecture. Due to the expected decrease in performance when compared to the original circuit, the Mis improved and stabilized through the temperature range. The finalized MASH 2+1 M achieves 86.755 dB of Signal-to-Noise-and-Distortion Ratio (SNDR) with 2 kHz, 300 mV input signal while using an active silicon area of 96439.127 μm2 or around 0.0964 mm2 (this active area does not contain the Digital Cancellation Logic (DCL) circuitry). | pt_PT |
| dc.identifier.uri | http://hdl.handle.net/10362/76572 | |
| dc.language.iso | eng | pt_PT |
| dc.subject | Analog to Digital Converter (ADC) | pt_PT |
| dc.subject | Multi-stAge Noise SHaping (MASH) | pt_PT |
| dc.subject | Sigma-Delta Modulator | pt_PT |
| dc.subject | Ultra Incomplete Settling (UIS) | pt_PT |
| dc.subject | Switched-Capacitor (SC) | pt_PT |
| dc.subject | Passive Integrator | pt_PT |
| dc.title | An Ultra Low Power Amplifier-less Sigma-Delta Modulator for Audio Applications | pt_PT |
| dc.type | master thesis | |
| dspace.entity.type | Publication | |
| rcaap.rights | openAccess | pt_PT |
| rcaap.type | masterThesis | pt_PT |
| thesis.degree.name | Mestre em Engenharia Eletrotécnica e de Computadores | pt_PT |