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Title: Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC
Author: Goes, J.
Esperança, B.
Tavares, R.
Galhardo, A.
Paulino, N.
Silva, M. Madeiros
Issue Date: Mar-2008
Publisher: IEEE
Abstract: This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and simulations demonstrate that a THD of –79 dB and an ENOB better than 12 bits can be reached without self-calibration.
Description: IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA
Appears in Collections:FCT: DEE - Documentos de conferências internacionais

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