Sigma-Delta Modulators with Passive RC Integrators: Theory, Design Methodology for Optimization and Silicon Results

Abstract

In this Thesis, energy and area efficient techniques are discussed and a CT SDM, with 27.5 fJ/conv.-step of energy efficiency, employing passive RC integrators is presented. Between each passive RC integrator a simple differential pair is added, as low-gain open-loop amplifier, and most of the loop gain is obtained in the 1-bit comparator. Nevertheless, the processing gain is limited by the comparator’s noise due to the low voltage swing at the input of this building block. In order to maximize the performance, and due to a large number of trade-offs, such as the nonlinear behavior of the 1-bit quantizer that drastically affects the NTF (specially with low input signals), the circuit has been designed with a systematic design methodology, also proposed in this thesis based on a genetic algorithm (GA). Moreover, and due to the trade-off between RC variations and loop stability, the modulator is also optimized taking this undesired behavior in consideration, avoiding the need for any self-calibration. The 65 nm CMOS SDM prototype designed, implemented and experimentally evaluated during this research work, occupies only 0.013 mm2, dissipates 256 mWfrom a 0.7 V supply, and it achieves a peak SNDR of 69.1 dB in a 2 MHz bandwidth (BW). The dynamic range (DR) reaches 76.2 dB, which corresponds to a Schreier figure-of-merit (FoMSchreier) of 175.1 dB. To the best of the author’s knowledge, the proposed modulator is the most energy- and area-efficient designs published thus far1, considering SDMs with BWs larger than 50 kHz published at the two flagship conferences requiring silicon demonstration, namely, IEEE ISSCC and IEEE Symposium on VLSI Circuits [1].