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Projeto de investigação
AdaPtive micROfluidic- and nano-enabled smart systems for waTEr qUality Sensing
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Design of a Fully Integrated Power Management Unit with a Multi-ratio and Multi-cell Switched-Capacitor DC-DC Converter
Publication . Madeira, Ricardo Falé de Carvalho; Paulino, Nuno; Oliveira, João
The Internet of Things (IoT) smart nodes deployment have been increasing rapidly in recent years, in a wide range of applications. These nodes are typically inserted in Wireless Sensor Networks (WSN), ranging from a few numbers to hundreds of nodes. Solutions using System-on-Chip (SoC) have been proposed for the nodes implementation, due to their low production costs. One import block of these SoCs is the Power Management Unit (PMU), used to power the node. Since the available energy is limited, efficient energy conversion is crucial to reduce the maintenance costs. To this end, Switched-Capacitor (SC) DC-DC converters have been proposed, since they can be fully integrated in CMOS technology, and offer a good trade-off between efficiency and power density. This thesis describes the design and test of two PMU Integrated Circuit (IC) prototypes in 130 nm bulk CMOS technology. The first is a 1 mW PMU composed by a multi-ratio SC converter with three voltage Conversion Ratios (CRs) 1/2, 2/3, and 1/1, covering an input voltage range of 1.1 V to 2.3 V, and generating a 0.9 V output voltage. It also includes a set of auxiliary circuits including a phase generator, a CR controller, the switch drivers, and a start-up circuit. The total circuit active area is 0.138 mm2 and a peak efficiency of 80.4% was measured. The second prototype is a fully integrated 16 mW PMU which includes a multi-ratio 1+3 binary-weighted SC converter, including the same CRs, and the same input voltage range and output voltage value of the previous prototype. The PMU is now completely fully integrated by removing the external decoupling capacitor and by integrating the voltage reference generator, both external in the first prototype. The decoupling capacitor was removed by employing a time interleaving scheme and by using capacitance modulation, according with the output power level and input voltage value, sensed through the clock frequency. The PMU includes the first prototype re-designed auxiliary circuits plus a cell controller and voltage reference generator. The total circuit active area is 5.12 mm2 and a peak efficiency of 74.3% was measured.
Experimental set-up for an IoT power supply with an 130 nm SC DC-DC converter
Publication . Madeira, Ricardo; Correia, Nuno; Oliveira, João P.; Paulino, Nuno; UNINOVA-Instituto de Desenvolvimento de Novas Tecnologias; CTS - Centro de Tecnologia e Sistemas; DEE - Departamento de Engenharia Electrotécnica e de Computadores; DEE2010-A2 Electrónica
This paper presents an experimental set-up for performing preliminary tests for energy power systems, such as the ones found in the IoT systems. It is composed by an energy harvesting device that charges a supercapacitor and a Switched Capacitor (SC) DC-DC converter, implemented in 130 nm bulk CMOS technology, to convert the voltage variation of the supercapacitor into a stable power supply for the IoT system. The experimental results show that the SC DC-DC converter achieves a maximum energy efficiency of 75%, and the overall system achieves a maximum energy efficiency of 47%.
A Paradigm Shift in the Design of Analog Circuits Targeting Nanoscale CMOS and Large-scale TFT Technologies
Publication . Correia, Ana Paula Pinto; Goes, João; Barquinha, Pedro
Despite the strong developments in complementary metal-oxide-semiconductor (CMOS) or non-CMOS technologies such as, in oxide thin-film transistors (TFTs), their nonidealities and constraints impact on the circuits performance. This aspect is even more relevant in complex circuits, such as in analog-to-digital converters (ADCs), where the design is thorough. Then, using techniques capable to attenuate the impact of these limitations such as, negative feedback, or recurring to almost passive or digital (synthesizable and scalable) circuitry, it is possible to design outstanding ADCs in different technologies. Therefore, two ADCs were designed in this work, using two distinct technologies.
A Digital-delta-modulator (DM) with noise-shaping (NS) was designed using a deep-nanoscale CMOS technology. Employing almost passive and digital-circuitry, this topology comprises a split-capacitor 10-bit digital-to-analog converter (DAC) with embedded sample-and-hold (S/H), a pseudo-differential inverter-based switched-capacitor (SC) integrator with a fully-passive SC common mode feedback (CMFB) circuit, a single-bit comparator, an accumulator and a clock and phase generators. Simulations revealed a signal-to-noise-and-distortion ratio (SNDR) close to 74 dB, a 12-bit effective number of bits (ENOB), with a Walden figure-of-merit (FoM), FoMWalden, of 12.5 fJ/conv.-step.
Using oxide TFTs, a 2nd-order delta-sigma modulator (DSM) was designed. Given the technology limitations, an almost passive structure was considered, with a design that relied essentially on the comparator project. During schematic simulations, a SNDR close to 69 dB, corresponding to an ENOB of ≈ 11:3-bit, was achieved (FoMWalden of 40 nJ/conv.-step). After the fabrication, individual transistors were characterised but they provided completely different electrical properties from the devices used to create the simulation model. The circuits, where comparators are included, were also measured but fabrication problems were detected. Strategies to mitigate these effects are currently being implemented.
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European Commission
Programa de financiamento
H2020
Número da atribuição
644852