Utilize este identificador para referenciar este registo: http://hdl.handle.net/10362/89449
Título: A Comparitive Study of On-Chip Clock Generators Using a-IGZO TFTs for Flexible Electronic Systems
Autor: Wadhwa, Nishtha
Martins, Jorge
Bahubalindruni, Pydi
Deb, Sujay
Barquinha, Pedro
Palavras-chave: A-IGZO TFTs
Bootstrapping
Flexible on-chip clock generator
Pseudo-CMOS
Ring Oscillator
Electrical and Electronic Engineering
Instrumentation
Data: 19-Dez-2018
Editora: Institute of Electrical and Electronics Engineers (IEEE)
Citação: Wadhwa, N., Martins, J., Bahubalindruni, P., Deb, S., & Barquinha, P. (2018). A Comparitive Study of On-Chip Clock Generators Using a-IGZO TFTs for Flexible Electronic Systems. In 2018 International Flexible Electronics Technology Conference, IFETC 2018 Article 8583926 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/IFETC.2018.8583926
Resumo: This paper presents a comparitive study of ring oscillators (RO) using amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistors (TFTs) to implement on-chip clock generator for flexible electronic systems. A five-stage RO has been implemented with different inverter topologies using IGZO TFTs, which includes Diode connected load, Capacitive bootstrapping (BS), Pseudo-CMOS and Pseudo-CMOS bootstrapping architectures. These topologies have been simulated using in-house IGZO TFT models under similar conditions using different power supplies (10 V, 15 V and 20 V) in cadence environment. Among all architechtures Capacitive bootstrapping RO has ensured highest frequency of operation in the order of MHz and an output swing of 82% of V DD . Whereas, Pseudo-CMOS based RO provides the lowest power consumption in the order of μW with an output swing of 57% of V DD . On the other hand, the combination of Pseudo CMOS and bootstrapping has ensured highest voltage swing of 95% of V DD . In terms of power delay product (PDP) BS RO is superior with respect to other topologies. This work provides a clear insight to the designer to choose a particular topology for given application, mainly for on-chip clock generation for flexible electronic systems based on the requirements.
Descrição: ECR/2017/000931. POCI-01-0145-FEDER-007688. No. 692373 (BET-EU). SFRH/BD/122286/2016.
Peer review: yes
URI: http://www.scopus.com/inward/record.url?scp=85060726683&partnerID=8YFLogxK
DOI: https://doi.org/10.1109/IFETC.2018.8583926
ISBN: 9781538633571
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