Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

Goes, J.; Paulino, N.; Galhardo, A.

http://hdl.handle.net/10362/4037

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Autores

Goes, J.

Paulino, N.

Galhardo, A.

Resumo(s)

A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme.

Descrição

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA

URI

http://hdl.handle.net/10362/4037

Editora

IEEE

Coleções

FCT: DEE - Artigos em revista internacional com arbitragem científica

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