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Infinite Impulse Response Configurable Filter
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Em sistemas modernos de comunicação e processamento de sinais, PLLs são
essenciais para a síntese de frequência, sincronização e supressão de desvios. Com o
escalonamento contínuo da tecnologia, as ADPLLs tornaram-se cada vez mais atraentes
devido à sua programação, robustez e potencial de integração. No entanto, o filtro de loop
digital continua a ser um bloco crítico, pois sua implementação afeta diretamente a
estabilidade do loop e a pureza espectral. Neste trabalho, é desenvolvido um filtro de loop
digital IIR para uma ADPLL. Os coeficientes de filtro são derivados de um modelo analógico
tipo II PLL que usa a transformada bilinear e mapeados em duas formas: teórica (real) e
inteira. Essa representação dupla leva em conta restrições de hardware, como resolução
limitada e largura de entrada finita. O filtro foi implementado e validado através de um fluxo
de verificação multinível compreendendo simulações comportamentais, modelagem RTL,
cosimulações de sinal misto com nível de transistor e simulações pós-layout incluindo
parasitas, usando 16 nm célula padrão, resultando em uma área de 970.704 𝜇m2 para o
filtro de loop, e 91.325 𝜇m2 para o DSM. Os resultados de simulação mostraram que a
formulação analítica inicial, designada por Modelo Teórico 1, conduz a um desvio da
frequência natural quando comparada com o comportamento observado em simulação.
Esta discrepância motivou o desenvolvimento de uma formulação refinada, o Modelo
Teórico 2, através da inclusão de um fator de correção. Com o Modelo Teórico 2, as
previsões analíticas apresentam uma concordância significativamente mais próxima com a
dinâmica loop obtida por simulação, particularmente no que diz respeito à frequência
natural. As implementações inteiras utilizando netlists extraídos do layout do filtro de loop e
do DSM demonstram um comportamento consistente com as previsões do Modelo Teórico
2, apesar das limitações associadas ao comprimento finito de palavra. O DSM revelou-se
indispensável: quando ativado, suprimiu o ruído de quantização, melhorou a qualidade do
sinal de controlo do DCO e permitiu que a saída do ADPLL se aproximasse mais do caso
ideal. As co-simulações pós layout introduziram não idealidades realistas e efeitos
parasíticos, que resultaram em alguns xi desvios na margem de fase e introduziram
variações de fase na resposta do loop. Em suma, este trabalho demonstra que um filtro IIR
digital pode ser integrado numa ADPLL, sublinhando a importância do mapeamento dos
coeficientes e o papel crítico do DSM.
In modern communication and signal processing systems, Phase Locked Loop (PLL)s are essential for frequency synthesis, synchronization, and jitter suppression. With the continued scaling of technology, All Digital Phase Locked Loop (ADPLL)s have become increasingly attractive due to their programmability, robustness, and integration potential. However, the digital loop filter remains a critical block, as its implementation directly impacts loop stability and spectral purity. In this work, the development of a Infinite Impulse Response (IIR) digital loop filter for an ADPLL is presented. The filter coefficients are derived from an analog type II PLL model using the bilinear transform and mapped into two forms: theoretical (real) and integer. This dual representation accounts for hardware constraints such as limited resolution and finite input width. The filter was implemented and validated through a multilevel verification flow comprising behavioral simulations, Register Transfer Level (RTL) modeling, mixed-signal cosimulations with transistor-level, and post-layout simulations including parasitics, using 16 𝜇m standard cell, resulting in an area of 970.704 𝜇m2 for the loop filter, and 91.325 𝜇m2 for the Delta Sigma Modulator (DSM). Simulation results showed that the initial analytical formulation, referred to as Theoretical Model 1, leads to a shift in the natural frequency when compared with the behavior observed in simulation. This discrepancy motivated the development of a refined formulation, Theoretical Model 2, through the inclusion of a correction factor. With theoretical model 2, the analytical predictions exhibit a significantly closer agreement with the simulated loop dynamics, particularly regarding the natural frequency. Integer implementations using layout-extracted netlists of the loop filter and DSM demonstrate behavior consistent with the predictions of theoretical model 2, despite finite word-length limitations. The DSM was shown to be indispensable: when enabled, it suppressed quantization noise, improved the quality of the Digital Controlled Oscillator (DCO) control signal, and allowed the ADPLL output to more closely approach the ideal case. Post layout co-simulations introduced realistic non idealities and parasitic effects, which result in some deviations in phase margin and introduce phase deviations in the loop response. ix Overall, this work demonstrates that a digital IIR loop filter can be integrated into ADPLLs, underlining the importance of coefficient mapping and the critical role of the DSM.
In modern communication and signal processing systems, Phase Locked Loop (PLL)s are essential for frequency synthesis, synchronization, and jitter suppression. With the continued scaling of technology, All Digital Phase Locked Loop (ADPLL)s have become increasingly attractive due to their programmability, robustness, and integration potential. However, the digital loop filter remains a critical block, as its implementation directly impacts loop stability and spectral purity. In this work, the development of a Infinite Impulse Response (IIR) digital loop filter for an ADPLL is presented. The filter coefficients are derived from an analog type II PLL model using the bilinear transform and mapped into two forms: theoretical (real) and integer. This dual representation accounts for hardware constraints such as limited resolution and finite input width. The filter was implemented and validated through a multilevel verification flow comprising behavioral simulations, Register Transfer Level (RTL) modeling, mixed-signal cosimulations with transistor-level, and post-layout simulations including parasitics, using 16 𝜇m standard cell, resulting in an area of 970.704 𝜇m2 for the loop filter, and 91.325 𝜇m2 for the Delta Sigma Modulator (DSM). Simulation results showed that the initial analytical formulation, referred to as Theoretical Model 1, leads to a shift in the natural frequency when compared with the behavior observed in simulation. This discrepancy motivated the development of a refined formulation, Theoretical Model 2, through the inclusion of a correction factor. With theoretical model 2, the analytical predictions exhibit a significantly closer agreement with the simulated loop dynamics, particularly regarding the natural frequency. Integer implementations using layout-extracted netlists of the loop filter and DSM demonstrate behavior consistent with the predictions of theoretical model 2, despite finite word-length limitations. The DSM was shown to be indispensable: when enabled, it suppressed quantization noise, improved the quality of the Digital Controlled Oscillator (DCO) control signal, and allowed the ADPLL output to more closely approach the ideal case. Post layout co-simulations introduced realistic non idealities and parasitic effects, which result in some deviations in phase margin and introduce phase deviations in the loop response. ix Overall, this work demonstrates that a digital IIR loop filter can be integrated into ADPLLs, underlining the importance of coefficient mapping and the critical role of the DSM.
Descrição
Palavras-chave
Digital Loop Filter IIR DSM ADPLL Type II PLL Bilinear Transform