Paulino, NunoGarcia, Pedro Miguel Lobato2020-09-112020-09-112020-072020http://hdl.handle.net/10362/103893This thesis addresses the problem of voice recognition, by studying how to build a lowcost solution for data acquisition, presents the analysis, design implementation and simulation of a low-cost continuous-time(CT) passive sigma-delta modulator(SDM) with signal-to-noise-plus-distortion ratio(SNDR) > 86dB to increase fidelity in voice recognition applications. Employing passive RC integrators and a differential signal structure, the CT passive SDM is optimized to work as independently from a specific comparator module as possible, by decreasing the necessary gain of the comparator in the modulator gain. Nevertheless, the loop gain is restricted by the comparator’s noise, aggravated by the high attenuation of the passive RC integrators on the signal, causing low voltage swing at the comparator’s input. It is discussed the viability of utilizing a microprocessor (μP) as substitute of the comparator block in a CT passive SDM, specifically, the esp32. Due to hardware limitations and the high-frequency requirements of the CT passive SDM, it is proven this substitution is not viable. Along the course of the design implementation a comparison in the performance of three different simulation software is presented, these software being, the open-source LTspice VII, the open-source Ngspice and the private Cadence Virtuoso. As it was necessary to change simulation software at different stages in the design of the circuit.engmaster thesis