Faculdade de Ciências e Tecnologia (FCT) >
FCT Departamentos >
FCT: Departamento de Engenharia Electrotécnica >
FCT: DEE - Dissertações de Mestrado >
Please use this identifier to cite or link to this item:
|Título: ||Pipelined analog-to-digital conversion using current-mode reference shifting|
|Autor: ||Silva, Alexandre Herculano Mendes|
|Orientador: ||Goes, João|
|Palavras-chave: ||Analog-to-Digital Converter (ADC),|
Current-mode reference shifting
CMOS current reference
pipelined A/D conversion
|Issue Date: ||2012|
|Editora: ||Faculdade de Ciências e Tecnologia|
|Resumo: ||Pipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high resolution applications. A fundamental, but often unreferenced building block of pipeline ADCs are the reference voltage circuits. They are required to maintain a stable reference with low output impedance to drive large internal switched capacitor loads quickly. Achieving this usually leads to a scheme that consumes a large portion of the overall power and area. A review of the literature shows that the required stable reference can be achieved with either on-chip buffering or with large off-chip decoupling capacitors. On-chip buffering is ideal for system integration but requires a high speed buffer with high power dissipation. The use of a reference with off-chip decoupling results in significant power savings but increases the pads of chip, the count of external components and the overall system cost. Moreover the amount of ringing on the internal reference voltage caused by the series inductance of the package makes this solution not viable for high speed ADCs.
To address this challenge, a pipeline ADC employing a multiplying digital-to-analog converter (MDAC) with current-mode reference shifting is presented. Consequently, no reference voltages and, therefore, no voltage buffers are necessary. The bias currents are generated on-chip by a reference current generator that dissipates low power.
The proposed ADC is designed in a 65 nm CMOS technology and operates at sampling rates ranging from 10 to 80 MS/s. At 40 MS/s the ADC dissipates 10.8 mW from a 1.2 V power supply and achieves an SNDR of 57.2 dB and a THD of -68 dB, corresponding to an ENOB of 9.2 bit. The corresponding figure of merit is 460 fJ/step.|
|Descrição: ||Dissertação para obtenção do grau de Mestre em
Engenharia Electrotécnica e de Computadores|
|Appears in Collections:||FCT: DEE - Dissertações de Mestrado|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.