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Please use this identifier to cite or link to this item: http://hdl.handle.net/10362/4060

Título: A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification
Autor: Goes, J.
Oliveira, J. P.
Paulino, N.
Fernandes, J.
Paisana, J.
Palavras-chave: Parametric amplification
High-speed
Low-power
Analog-to-digital converter
Multiplying-by-two amplifier
Issue Date: May-2008
Editora: Department of Microelectronics & Computer Science, Technical University of Lodz
Resumo: In this paper a new structure for a multiplying-by-two amplifier is proposed. It is implemented by switching MOS capacitors with floating sources from inversion into depletion dropping the capacitance values in the amplification phase. Low-power is achieved since no operational amplifiers are required but, instead, simple sourcefollowers are used to provide the required isolation. Simulation results show that linearity levels better than 60dB and gain accuracies of better than 1.6% are achieved making this circuit well suited to be used in ultra low-power highspeed 6-to-8 bits pipeline or multi-stage algorithmic ADCs.
Descrição: 15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia
URI: http://hdl.handle.net/10362/4060
Appears in Collections:FCT: DEE - Documentos de conferências internacionais

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