Please use this identifier to cite or link to this item:
Title: New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification
Authors: Goes, J.
Oliveira, J. P.
Paulino, N.
Fernandes, J.
Paisana, J.
Issue Date: Aug-2008
Publisher: IEEE
Abstract: In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique.
Description: 15th IEEE International Conference on Electronics, Circuits and Systems, Malta
Appears in Collections:FCT: DEE - Documentos de conferências internacionais

Files in This Item:
File Description SizeFormat 
Goes_2008.pdf271,5 kBAdobe PDFView/Open

FacebookTwitterDeliciousLinkedInDiggGoogle BookmarksMySpace
Formato BibTex MendeleyEndnote Degois 

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.