|
RUN >
Faculdade de Ciências e Tecnologia (FCT) >
FCT Departamentos >
FCT: Departamento de Engenharia Electrotécnica >
FCT: DEE - Artigos em revista internacional com arbitragem científica >
Please use this identifier to cite or link to this item:
http://hdl.handle.net/10362/4037
|
| Title: | Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback |
| Authors: | Goes, J.
Paulino, N.
Galhardo, A. |
| Issue Date: | Apr-2008 |
| Publisher: | IEEE |
| Abstract: | A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly
attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme. |
| Description: | IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA |
| URI: | http://hdl.handle.net/10362/4037 |
| Appears in Collections: | FCT: DEE - Artigos em revista internacional com arbitragem científica
|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
|
